1 cat93HC46 1k-bit high speed microwire serial eeprom features high speed operation: ?93HC46: 3mhz low power cmos technology 1.8 to 6.0 volt operation selectable x8 or x16 memory organization self-timed write cycle with auto-clear sequential read software write protection power-up inadvertent write protection 1,000,000 program/erase cycles 100 year data retention commercial, industrial and automotive temperature ranges 93c46/56/57/66/86 f02 pin configuration dip package (p) soic package (j) technology. the device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. the cat93HC46 is available in 8-pin dip, 8-pin soic or 8-pin tssop packages. description the cat93HC46 is a 1k-bit serial eeprom memory devices which is configured as either registers of 16 bits (org pin at v cc ) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93HC46 is manufactured using catalyst? advanced cmos eeprom floating gate soic package (s) pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +1.8 to 6.0v power supply gnd ground org memory organization nc no connection pe* program enable block diagram note: when the org pin is connected to vcc, the x16 organization is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. ?2002 by catalyst semiconductor, inc. characteristics subject to change without notice tssop package (u) cs sk di do v cc nc org gnd 1 2 3 4 8 7 6 5 v cc cs sk org gnd do di 1 2 3 4 8 7 6 5 cs sk di do v cc org gnd 1 2 3 4 8 7 6 5 nc nc 8 7 6 5 v cc org gnd di cs sk do 1 2 3 4 nc doc. no. 1008,rev. c v cc address decoder memory array organization data register mode decode logic clock generator output buffer do sk cs di org gnd
2 cat93HC46 doc. no. 1008, rev. c absolute maximum ratings* temperature under bias ................. 55 c to +125 c storage temperature ....................... 65 c to +150 c voltage on any pin with respect to ground (1) ............ 2.0v to +v cc +2.0v v cc with respect to ground ............... 2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 note: (1) the minimum dc input voltage is 0.5v. during transitions, inputs may undershoot to 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from 1v to v cc +1v. (5) standby current (isb 2 )=0 a (<900na). d.c. operating characteristics (over recommended operating conditions, unless otherwise specified.) limits symbol parameter min. typ. max. units test conditions i cc1 power supply current 3 ma f sk = 3mhz (operating write) v cc = 5.0v i cc2 power supply current 500 af sk = 3mhz (operating read) v cc = 5.0v i sb1 power supply current 10 a cs = 0v (standby) (x8 mode) org=gnd i sb2 (5) power supply current 0 a cs=0v (standby) (x16mode) org=float or v cc i li input leakage current 1 av in = 0v to v cc (including org pin) i lo output leakage current 1 av out = 0v to v cc , (including org pin) cs = 0v v il1 input low voltage -0.1 0.8 4.5v v cc < 5.5v v ih1 input high voltage 2 v cc + 1 4.5v v cc < 5.5v v il2 input low voltage 0 v cc x 0.2 1.8v v cc < 4.5v v ih2 input high voltage v cc x 0.7 v cc + 1 1.8v v cc < 4.5v v ol1 output low voltage 0.4 4.5v v cc < 5.5v, i ol =2.1ma v oh1 output high voltage 2.4 v 4.5v v cc < 5.5v, i oh = -400ma v ol2 output low voltage 0.2 1.8v v cc < 4.5v, i ol =1ma v oh2 output high voltage v cc -0.2 1.8v v cc < 4.5v, i oh = -100 a v v v v v v
3 cat93HC46 doc. no. 1008, rev. c pin capacitance symbol test max. units conditions c out (1) output capacitance (do) 5 pf v out =0v, t a =25 ? c, f sk =1mhz c in (1) input capacitance (cs, sk, di, org) 5 pf v in =0v, t a =25 ? c, f sk =1mhz note: (1) this parameter is tested initially and after a design or process change that affects the parameter. instruction set start address data instruction bit opcode x8 x16 x8 x16 comments read 1 10 a6-a0 a5-a0 read address an a0 erase 1 11 a6-a0 a5-a0 clear address an a0 write 1 01 a6-a0 a5-a0 d7-d0 d15-d0 write address an a0 ewen 1 00 11xxxxx 11xxxx write enable ewds 1 00 00xxxxx 00xxxx write disable eral 1 00 10xxxxx 10xxxx clear all addresses wral 1 00 01xxxxx 01xxxx d7-d0 d15-d0 write all addresses recommended operating conditions temperature minimum maximum commercial 0 ? c +70 ? c industrial -40 ? c +85 ? c automotive -40 ? c +105 ? c extended -40 ? c +125 ? c device supply voltage range cat93HC46 2.5v to 6.0v cat93HC46-1.8 1.8v to 6.0v
4 cat93HC46 doc. no. 1008, rev. c limits v cc =v cc =v cc = 1.8v-6v 2.5v-6v 4.5v-5.5v test symbol parameter min. max. min. max. min. max. units conditions t css cs setup time 200 100 50 ns t csh cs hold time 0 0 0 ns v il = 0.45v t dis di setup time 400 200 50 ns v ih = 2.4v t dih di hold time 400 200 50 ns c l = 100pf t pd1 output delay to 1 1 0.5 0.1 sv ol = 0.8v t pd0 output delay to 0 1 0.5 0.1 sv oh = 2.0v t hz (1) output delay to high-z 400 200 100 ns t ew program/erase pulse width 5 5 5 ms t csmin minimum cs low time 1 0.5 0.1 s t skhi minimum sk high time 1 0.5 0.1 s t sklow minimum sk low time 1 0.5 0.1 s t sv output delay to status valid 1 0.5 0.1 sc l = 100pf sk max maximum clock frequency dc 250 dc 1000 dc 3000 khz power-up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms a.c. characteristics note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (3) the input levels and timing reference points are shown in ac test conditions table. a.c. test conditions input rise and fall times 50ns input pulse voltages 0.4v to 2.4v 4.5v v cc 5.5v timing reference voltages 0.8v, 2.0v 4.5v v cc 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v v cc 4.5v timing reference voltages 0.5v cc 1.8v v cc 4.5v c l = 100pf (3)
5 cat93HC46 doc. no. 1008, rev. c device operation the cat93HC46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. the cat93HC46 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9-bit instructions control the reading, writing and erase operations of the device. when organized as x8, seven 10-bit instructions control the reading, writing and erase operations of the device. the cat93HC46 operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. figure 1. sychronous data timing figure 2a. read instruction timing sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do t cs standby t hz high-z high-z 11 0 a n a n 1 a 0 0 d n d n 1 d 1 d 0 t pd0 min
6 cat93HC46 doc. no. 1008, rev. c the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organizations). read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93HC46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ) after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the cat93HC46 will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/busy status of the cat93HC46 can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking figure 3. write instruction timing 93c46/56/57/66/86 f05 figure 2b. sequential read instruction timing sk cs di do t cs min standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk cs di do high-z 11 0 a n a n 1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 1 11 1 111 11111111 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care
7 cat93HC46 doc. no. 1008, rev. c clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/ busy status of the cat93HC46 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. erase/write enable and disable the cat93HC46 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93HC46 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/ disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. (note 1.) the ready/busy status of the cat93HC46 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93HC46 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. note 1: after the last data bit has been sampled, chip select (cs) must be brought low before the next rising edge of the clock (sk) in order to start the self-timed high voltage cycle. this is important because if the cs is brought low before or after this specific frame window, the addressed location will not be programmed or erased. figure 4. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs min 11 a 0
8 cat93HC46 doc. no. 1008, rev. c figure 7. wral instruction timing figure 5. ewen/ewds instruction timing figure 6. eral instruction timing sk cs di standby 10 0 * * enable=11 disable=00 sk cs di do standby t cs min high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t cs min d n d 0 0 0
9 cat93HC46 doc. no. 1008, rev. c ordering information notes: (1) the device used in the above example is a 93HC46si-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel) package p = pdip s = soic (jedec) j = soic (jedec) u = tssop prefix device # suffix 93HC46 s i te13 product number 93HC46: 1k tape & reel te13: 2000/reel operating voltage blank (v cc =2.5 to 6.0v) 1.8 (v cc =1.8 to 6.0v) -1.8 cat temperature range blank = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) a = automotive (-40 c to +105 c) optional company id e = extended (-40 ? c to +125 ? c)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 1008 revison: c issue date: 3/29/02 type: final
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